Sense amplifiers are commonly used in semiconductor memory devices to sense and amplify a potential difference between paired bit lines. FIG. 1 shows a circuit diagram of the latch portion of a conventional sense amplifier, indicated generally at 4, formed by N-channel transistors M.sub.1 and M.sub.2 and P-channel transistors M.sub.3 and M.sub.4 where N.sub.1 and N.sub.2 are the paired bit lines, NC is the N-channel drive line, and PC is the P-channel drive line.
It is a generally desirable goal in semiconductor fabrication to reduce the size of semiconductor devices. This holds true for semiconductor memory devices such as Dynamic Random Access Memory (DRAM) devices. In a typical DRAM device, a sense amplifier must fit in the width of two bit line pairs which limits the sense amplifier width to four times the bit line pitch. This limitation on the pitch of sense amplifiers also limits the width of the sense amplifier latch transistors.
As the latch transistor width decreases, the sensing speed and performance of the sense amplifier also decreases. Thus, in a conventional memory device, the pitch of the memory bit lines limits the performance of the sense amplifiers by limiting the width of the latch transistors.